Ulrich Drepper


Ulrich Drepper joined Red Hat again in 2017, after a seven-year hiatus. He is and during his previous stint also was a member of the office of the CTO. In that capacity, he is looking at upcoming technologies for products and internal application. His focus is mostly on machine learning and low-level/high-performance computing as well as alternative compute architectures.

Previously he worked at Goldman Sachs in the technology division. The last position was as a member of the data science research group, focusing on the development of models and various types of stochastic algorithms to aid in the operation of the technology division.

His main interests are in the areas of low-level technologies like machine and processor architectures, programming language, compilers, high-performance, and low-latency computing. In addition, he is interested in using statistics and machine learning for performance analysis or programs and security of application and OS environments. He worked on several revisions of the POSIX standard and was invited expert for both the C and C++ standard committees.

Ulrich received his Diploma in Informatics from the University of Karlsruhe, Germany.

Homepage: http://www.akkadia.org/drepper/.



C++ and Memory: Between Correctness and Performance (2018)

Memory handling was always a core problem of C/C++. As system programming languages direct control was needed and wanted. This clashes with programming practice which does not allow for time for meticulously planning and programmer's grasp and large, connected code bases.

This is why part of the agenda for the development of the C++ language for the last 10+ years was to fix or at least dramatically improve the memory handling, even for large code bases. The available techniques can make writing code as easy as with controlled runtimes but the price to pay can be significant.

This talk will introduce the available techniques for memory handling in C++ today and what is planned or thought about for the future. The implementations are explained and the resulting performance implications and other overhead is explained. C++ programmers will learn to how the language designers think modern C++ code should be written and make informed decisions when writing new code.


What are FPGAs and How Do They Work (2018)

Even though FPGAs have been around for a long time most developers don't know enough about them. While their predominant use was in the embedded realm they are used now as an alternative accelerator in server and desktop environments.

This talk will explain how and why FPGAs differ from normal processors. At the example of one FPGA the talk will introduce everything from the programming languages used, the tools to translate them, the binaries produced, and how the code finally gets executed.


Intelligent Application Configuration Data Management (2015)

It was a big step to allow programs to be customized for a specific situation by having configurations represented user-changable way. Unfortunately not much changed, especially for most non-GUI apps. The latter often have only very crude ways of steering once the process is running. In this talk I am showing how to create interfaces to a program’s configuration which provide a lot more flexibility than static files in /etc or whatever the equivalent is for the OS of your choice.


The Cost Of 64-bit Pointers (2015)

For many people “64 bits” are just plainly better than “32 bits”. The former is certainly a more recent development and, as such, has the potential of providing benefits. But not every program will unconditionally benefit. Measurements which show advantage often conflate the effects of multiple changes. In this talk we are looking at the individual changes of the ABIs, in particular the pointer size change, the contributions of the changes to performance, concentrating on the x86 architectures. I am showing ways to optimize performance with various techniques which can be selected to match the specific application. Some of the techniques will also be usable for non-x86 architectures.